3D LUT Altera® FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

As a part of the Video and Vision Processing (VVP) Suite Altera® FPGA IP, the 3D look-up table (LUT) Altera® FPGA IP provides an efficient solution for video color space and dynamic range conversions, chroma keying, and the creation of artistic effects.

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Key Features

Support up to 4 pixels in parallel (PIP) per clock processing.
Low subframe latency (21 clock cycles).
Support for 17³, 33³ and 65³ LUTs.
Support 3 and 4 output channels from the LUT (Alpha /key channel).
High-quality tetrahedral interpolation.
Independently set input/output pixel depth.
Independently set LUT precision.
Dynamic update of table values with optional double buffering to enable clean synchronous switching to a new LUT.
Includes ‘.cube’ file format conversion utility.
Support for 8, 10, 12, and 16-bit per color component.
Support resolutions up to 4K at 60 FPS on Cyclone® 10 FPGAs, Arria® 10 FPGAs, Stratix® 10 FPGAs, and Agilex® 5 FPGA E-Series.
Support resolutions up to 8K at 60 FPS on Agilex® 7 FPGAs and on Agilex® 5 FPGA D-Series.

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	Yes
Compliance	No
Development Language	Verilog, VHDL