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SDI II FPGA IP

Altera

The Altera SDI II FPGA IP core is a versatile solution for implementing serial digital interface (SDI) transmitters, receivers, or full-duplex links in FPGA-based systems. Supporting a wide range of video formats—from standard definition (SD) and high definition (HD) to 3G, 6G, and 12G rates—this IP core complies with SMPTE standards, making it ideal for professional broadcast and video infrastructure. It includes features such as automatic receiver rate detection and dynamic transceiver reconfiguration, enabling seamless adaptation to varying signal conditions and formats.

Key Features

  • Transceiver data interface: 20 bit, 40 bit, and 80 bit
  • Single Standard Support: Standard Definition or SD-SDI, High Definition or HD-SDI, 3 gigabits per second (Gbps) or 3G-SDI, Dual Link HD-SDI
  • Multiple Standard Support: Dual Standard up to HD-SDI, Triple Standard up to 3G-SDI, Multi Standard up to 12G-SDI
  • SMPTE support: SMPTE425M level A support (direct source image formatting), SMPTE425M level B support (dual link mapping)
  • Payload identification packet insertion and extraction
  • Clock enable generator
  • Video rate detection
  • Cyclic redundancy check (CRC) encoding and decoding (except SD)
  • Dual link data stream synchronization (only HD)
  • Note: Not all devices support all formats, see “General Description” in the IP Core Overview found in the User Guide.
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Development Language Encrypted Verilog, Encrypted VHDL

Encrypted Verilog source code

Design Examples

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

Market Segment and Sub-Segments