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H.264 Baseline, Main and High Profiles Single- and Multi-channel Encoder IP Core

Alma Technologies S.A.

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The H264-HP-E core from Alma Technologies is an advanced and self-contained ITU-T H.264 High profiles hardware encoder. This core is available in Intra-only [IDR], Light Motion Estimation [LME] and Full Motion Estimation [FME] prediction engine configurations. It supports real time encoding of both single and multiple 4:2:0 and 4:2:2 video streams, in 8-, 10- or 12-bit per component color depth, up to Profile Level 5.2. Encoding in the Constrained Baseline and Main profiles is also supported.

The encoder accepts the uncompressed video data in planar, interleaved, or macroblock scan format. It outputs standalone, standard compliant, Annex B NAL byte stream. No post processing on the output stream, other than (for example) storing, muxing or transmitting, is required. The output NAL byte stream can be decoded, as is, by any ITU-T H.264 compliant decoder that satisfies the Level requirements of the stream and conforms to the corresponding ITU-T H.264 profile.

The H264-HP-E core from Alma Technologies is an advanced and self-contained ITU-T H.264 High profiles hardware encoder. This core is available in Intra-only [IDR], Light Motion Estimation [LME] and Full Motion Estimation [FME] prediction engine configurations. It supports real time encoding of both single and multiple 4:2:0 and 4:2:2 video streams, in 8-, 10- or 12-bit per component color depth, up to Profile Level 5.2. Encoding in the Constrained Baseline and Main profiles is also supported.

The encoder accepts the uncompressed video data in planar, interleaved, or macroblock scan format. It outputs standalone, standard compliant, Annex B NAL byte stream. No post processing on the output stream, other than (for example) storing, muxing or transmitting, is required. The output NAL byte stream can be decoded, as is, by any ITU-T H.264 compliant decoder that satisfies the Level requirements of the stream and conforms to the corresponding ITU-T H.264 profile.

Key Features

  • Full compliance to the ITU-T H.264 specification
  • High 10, High 10 intra, High 4:2:2, High 4:2:2 intra, High 4:4:4 (12 bit 4:2:2 or 4:2:0), and High 4:4:4 intra (12 bit 4:2:2 or 4:2:0) profiles encoding
  • Multi-format 4:2:0 and 4:2:2 YCbCr digital video input
  • 8-, 10- and 12-bit per component sample depth encoding
  • Multi-channel encoding option available
  • ITU-T H.264 Annex B compliant NAL byte stream output
  • Profile Level up to 5.2
  • True H.264 compression efficiency and perceptually optimized Image Quality
  • No host CPU assisted, standalone operation
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Verilog, VHDL

Pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and Place & Route scripts

Ordering Information

Market Segment and Sub-Segments