JPEG-LS-D: Lossless & Near-Lossless JPEG-LS Decoder

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Computer Aided Software Technologies, Inc (dba CAST)

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The JPEG-LS-D core implements a highly efficient and low-power, lossless and near-lossless image decompression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

The decoder core can decompress any JPEG-LS stream or JPEG-LS payload of image container formats, such as DICOM (Digital Imaging and Communications in Medicine). It accepts compressed streams of images with up to 16-bit per color samples and up to four color components, in all widely used color subsampling formats. Supporting oversize image dimension parameters, the core can decode images with resolutions exceeding 64k x 64k pixels.

The JPEG-LS-D core implements a highly efficient and low-power, lossless and near-lossless image decompression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

The easy-to-use JPEG-LS-D core operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample depth) to the system, so that the decoded images are properly further processed and/or displayed. Application (APP) or comment (COM) marker segments—which are typically used to embed metadata in the compressed stream—are also passed to the system via a dedicated interface.

SoC integration is straightforward thanks to standardized AMBA® interfaces. The core accepts compressed data and outputs pixel data, frame format information, and APP or COM marker segments via AXI4-Stream interfaces, and it provides access to its control and status registers via a 32-bit APB interface. A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.

The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model.

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Key Features

JPEG-LS ISO/IEC 14495-1 support, w/ all encoding parameters (optional near lossless). More than 64Kx64K, up to 16 bits/color sample & up to 4 colors.
Easy to use and integrate: no programming or control from host, AMBA I/F (AXI4-Stream & APB), reporting image format & potential marker syntax errors.
1 sample/cycle - area opt. version (from 40K eq. gates, up to 350 Msamples/s). Synthesis-configurable samples/cycle - throughput opt. version.

Offering Brief

Device Family	Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted VHDL, Verilog