AES-CCM: Authenticated Encrypt/Decrypt Engine

Overview Key Features Offering Brief What's Included Ordering Information Markets

Computer Aided Software Technologies, Inc (dba CAST)

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The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.

Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.

CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt.

The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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Key Features

NIST-validated, realizes the AES Block Cipher, implemented according to NIST Special Publication 800-38D & employing Counter with CBC-MAC mode (CCM).
Processes 128-bit data in 32-bit blocks, employing user-programmable key size of 128, 192, or 256 bits.
Two architectures available: The Standard (32-bit datapath) and the Fast (128-bit datapath). The first is compact & the second offers high throughput.
Works with a pre-expanded key or can integrate the optional key expansion function.
Simple, fully synchronous, reusable design.
Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices.

Offering Brief

Device Family	Arria® 10 GX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, MAX® 10 FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Encrypted VHDL, Verilog, VHDL