JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Computer Aided Software Technologies, Inc (dba CAST)

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This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.

The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost-effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.

Once programmed, the easy-to-use decoder operates on a ...

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

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Key Features

ISO/IEC 10918-1 Baseline & Extended Dec, single-frame, up to 4 color components, 8- & 12-bit samples, several subsampling formats, up to 64kx64k.
Interfaces: AXI Streaming I/O data interfaces, APB Control/Status interface, optional AHB wrapper with DMA capabilities.
Synthesis-time configurable & scalable, offering very high throughput (max 32 samples/cycle), maximizing it when input streams produced by JPEG-EX-F.
Ease of Integration, requiring no programming or control, while it reports image format & marker syntax errors. Optional Block-to-Raster Conversion.

Offering Brief

Device Family	Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog