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CSENT-Rx: SENT/SAE J2716 Receiver

Computer Aided Software Technologies, Inc (dba CAST)

Member

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface, and the reset values for all its control registers are defined at synthesis time. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. An external metadata port allows the host system to add customized metadata (e.g. timestamps) into the received data stream. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. The generation of trigger pulses is controll...

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface, and the reset values for all its control registers are defined at synthesis time. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. An external metadata port allows the host system to add customized metadata (e.g. timestamps) into the received data stream. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. The generation of trigger pulses is controlled via a dedicated input pin, or via a control register. A set of handshaking signals facilitates the integration with an external DMA controller. An extended set of interrupt sources includes detection of calibration variation, timeout errors, frequency drift error, FIFO-related triggers, frames’ validity and numerous frame’s errors. The CSENT-RX core is designed with industry best practice, has been rigorously verified and is production proven.

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Key Features

  • SENT/SAE J2716 Receiver - Fast and Slow Channel - 4, 6 or 8-bit CRC checking - Programmable Glitch filter - All types of SENT Frames - Programmable data length (1 to 8 nibbles) for Fast Channel Frames - Short (8-bit data) and Enhanced (12- or 16-bit data) Message Formats for Slow Channel - Fast Channel data mapping to reduce host/CPU overhead - Customized metadata support - Supports inverted SENT protocol
  • Trigger Pulse for Synchronous Sensors - Allows up to four sensors (transmitters) to use the same physical SENT connection - Programmable trigger pulse length - Activated via software or hardware
  • Ease of Integration - 32-bit APB or AXI4-Lite interface, and comprehensive set of interrupts - Programmable reference counter to validate calibration pulses - Optional Receive FIFO of configurable size for Fast Channel data - Run-time programmable configuration registers - Synthesis-time defined reset values for all registers, enables data reception without control from host processor - LINT-clean, single-clock domain, scan-ready design
  • Deliverables - RTL source code or targeted FPGA netlist - System Verilog Testbench - Sample synthesis and simulation scripts - Documentation - IP XACT register definitions
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Offering Brief

Offering Brief

Device Family Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist

System Verilog testbench

Comprehensive documentation

Sample synthesis and simulation scripts

IPxact register models

Ordering Information

CSENT-Rx

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