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PCI-M32: 32-bit, 33 MHz PCI Master/Target

Computer Aided Software Technologies, Inc (dba CAST)

Member

The PCI-M32 is a master/target PCI interface IP core compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates at PCI clock frequencies up to 33 MHz. The interface includes both master and target capabilities and implements 64 bytes of PCI Configuration Space, expandable up to 256 bytes. The target interface supports up to six Base Address Registers (BARs) with both I/O and Memory decoding capabilities, ranging from 16 bytes to 2 GB.

Supported PCI commands include Configuration Read/Write, Memory Read/Write, Memory Read Multiple (MRM), Memory Read Line (MRL), and I/O Read/Write. The PCI-M32 builds on over 20 years of CAST’s PCI IP development experience and is designed for easy reuse and integration. It follows proven design methodologies that ensure efficient technology mapping and rapid implementation.

The core is available in synthesizable RTL or as a pre-synthesized FPGA netlist, and comes complete with everyt...

The PCI-M32 is a master/target PCI interface IP core compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates at PCI clock frequencies up to 33 MHz. The interface includes both master and target capabilities and implements 64 bytes of PCI Configuration Space, expandable up to 256 bytes. The target interface supports up to six Base Address Registers (BARs) with both I/O and Memory decoding capabilities, ranging from 16 bytes to 2 GB.

Supported PCI commands include Configuration Read/Write, Memory Read/Write, Memory Read Multiple (MRM), Memory Read Line (MRL), and I/O Read/Write. The PCI-M32 builds on over 20 years of CAST’s PCI IP development experience and is designed for easy reuse and integration. It follows proven design methodologies that ensure efficient technology mapping and rapid implementation.

The core is available in synthesizable RTL or as a pre-synthesized FPGA netlist, and comes complete with everything needed for successful integration and deployment.

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Key Features

  • PCI specification 2.3 compliant; 33 MHz performance 32-bit datapath
  • Full bus Master/Target functionality; Zero wait states burst mode
  • Single interrupt support
  • Type 0 Configuration space
  • Support of all Base Address Registers; Support of backend initiated target retry, disconnect and abort
  • Parity generation and parity error detection
  • DMA Controller Core supporting independent write and read operations available
  • Optional bridge / interface to AMBA/AHB or Avalon-MM
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Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog, VHDL

Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL or FPGA netlist

System Verilog Testbench

Comprehensive Documentation

Sample synthesis and simulation scripts

Ordering Information

PCI-M32

from Direct

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