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JPEG-E-S: Baseline JPEG Encoder

Computer Aided Software Technologies, Inc (dba CAST)

Member

This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with remarkably low processing latency.

The JPEG-E-S encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.

The compact encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs.

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in th...

This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with remarkably low processing latency.

The JPEG-E-S encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.

The compact encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs.

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.

Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

Key Features

  • Supports ISO/IEC 10918-1 Baseline JPEG, single-frame and Motion JPEG, 8-bit samples, up to 4 components, all scan configs, markers, and programmable tables.
  • Provides rate control for images and video, limiting individual frame sizes and regulating bit rate across multiple input frames for consistent compression.
  • Provides AXI Streaming I/O for data, APB interface for control and status, plus an optional AHB wrapper with DMA for flexible system integration.
  • Processes one encoded sample per clock cycle with a compact design, requiring about 5k LUTs, enabling high-performance, area-efficient JPEG encoding.
  • Processes one encoded sample per clock cycle with a compact design, requiring about 5k LUTs, enabling high-performance, area-efficient JPEG encoding.
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Offering Brief

Offering Brief

Device Family MAX® 10 FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Verilog

FPGA netlist

System Verilog testbench

Bit-Accurate Software Model

Comprehensive documentation

Sample synthesis and simulation scripts

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments