Creonic Doppler Channel

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Creonic GmbH

Select

The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introducing a shift frequency to samples as a phase offset. The IP was developed to allow the performance evaluation of a low-earth orbit (LEO) digital communication system. Unlike a software-based DSF generator, which might take several hours and even days to accomplish the stated purpose, a hardware-based DSF generator requires significantly less time. Runtime is reduced by several orders of magnitude.

View Partner Website

Partner Product Page

Contact Now

Contact Creonic GmbH

LeadSource

ASAP Account ID

Record Type Name

Key Features

Support for orbital heights (h) in the range from 200 to 2000 km
Support for carrier frequencies (fc) in the range from 137 to 2200 MHz
Support for sample frequencies (fs) in the range from 500 Ksps to 500 Gsps
Support variations in the initial elevation angle due to different latitudes, obstructions in the visibility region, and regulatory requirements

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	22.4.0
Development Language	C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

Ordering Information