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AES 256 XTS IP

DesignGateway Co., Ltd.

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AES256-XTS IP Core implements the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.

Key Features

  • Support AES-XTS mode
  • Support 256-bit key size
  • Support input data width128-bit
  • Support Ciphertext Stealing
  • Peak throughput rate at 128 Mbits/MHz
  • High-throughput, up to 44.8 Gbps @350MHz
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Stratix® 10 GX FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo Yes
Compliance No
Latest Quartus Version Supported 23.1.0
Development Language Encrypted VHDL

Encrypted IP core

Reference Designs Quartus Project

Ordering Information

Market Segment and Sub-Segments