AES 128 IP

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DesignGateway Co., Ltd.

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AES-128 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 11 clock cycles. It delivers 11.6 Mbps per MHz, achieving up to 4.65 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.

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Key Features

Support AES ECB mode standard.
Support 128-bit key size.
Support input data width128-bit.
Throughput rate at 11.6 Mbits/MHz.
Speed up to 4.65 Gbps @400MHz.
128-bit data calculation time is constant at 11 clock cycles.

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series
Offering Status	Production
Integrated Testbench	No
Evaluation License	No
Design Examples Available	Yes
Demo	Yes
Compliance	No
Latest Quartus Version Supported	23.1.0
Development Language	Encrypted VHDL