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100G UDP IP Core

iWave Global

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iWave’s UDP/IP Hardware Protocol Stack IP Core enables ultra-high-speed data transmission with minimal latency, offloading UDP encapsulation tasks from the host processor. Designed for FPGAs, this IP core is ideal for applications requiring high-throughput streaming, even in non-SoC or processor-less designs. The core supports line-rate data transfer up to 40Gbps, making it well-suited for applications in media streaming, real-time sensor processing, and high-performance communication systems.

Built around a user-friendly AXI interface, the UDP/IP Core integrates seamlessly into FPGA-based architectures and supports standard UDP/IP protocols. This hardware-centric solution significantly reduces CPU load while enhancing throughput and reliability in data-intensive applications. By enabling efficient transmission of user data through the network layer, iWave’s UDP/IP Core empowers developers with the infrastructure needed to implement scalable, real-time c...

iWave’s UDP/IP Hardware Protocol Stack IP Core enables ultra-high-speed data transmission with minimal latency, offloading UDP encapsulation tasks from the host processor. Designed for FPGAs, this IP core is ideal for applications requiring high-throughput streaming, even in non-SoC or processor-less designs. The core supports line-rate data transfer up to 40Gbps, making it well-suited for applications in media streaming, real-time sensor processing, and high-performance communication systems.

Built around a user-friendly AXI interface, the UDP/IP Core integrates seamlessly into FPGA-based architectures and supports standard UDP/IP protocols. This hardware-centric solution significantly reduces CPU load while enhancing throughput and reliability in data-intensive applications. By enabling efficient transmission of user data through the network layer, iWave’s UDP/IP Core empowers developers with the infrastructure needed to implement scalable, real-time communication between FPGA systems and network devices.

The IP Core’s flexibility and performance make it an ideal fit for advanced networking, broadcast, and defense systems where deterministic behavior, bandwidth efficiency, and low-latency communication are essential.

Key Features

  • IPV4 support without packet fragmentation
  • Supports GMII/RGMII/SGMII/XGMII/XLGMII interfaces
  • Easy integration with 100G Ethernet MAC
  • Configurable AXI Stream interface with 8bit, 32bit, 64bit, 128bit, 256bit and 512bit width for transmission & reception of user data
  • 32bit AXI4-Lite interface for handling control and status registers
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGAs and SoC FPGAs F-Series
Offering Status Production
Device OPN(s) on Board AGFB027R24C2I2V
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Demo No
Integrated Testbench No
Evaluation License No
Design Examples Available No
Compliance No
Latest Quartus Version Supported 24.2.0
Development Language Verilog

IP Core

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