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PCIe GEN6 PHY IP

Logic Fruit Global Technologies Inc

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Logic Fruit's PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures efficient data handling for demanding applications such as AI, ML, high-performance computing, and modern storage technologies. With scalable throughput and a focus on reliability, this PHY IP simplifies integration into high-speed, data-intensive use cases.

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Key Features

  • Supports PAM-4 signaling through FPGA transceivers (SerDes).
  • Supports PIPE 6.x (SerDes Architecture) for easy integration with Logic Fruit or any third party PCIe 6.x controller IP.
  • Supports PRBS testing including loopback modes.
  • Supports different power states as per PCIe PHY specification.
  • Supports 100MHz common reference clock between RC and EP.
  • Supports FPGA native features like DRP access, eye scan, PRBS / Test pattern generation and checker.
  • Supports PCIe-compliant patterns including Gen6 compliance/modified compliance (PCIe base 6.2 sections 4.2.14-15), 52UI jitter measurement (PCIe base 6.2 section 4.2.16), High swing toggle (PCIe base 6.2 section 4.2.17), Gen5 compliance/modified compliance (PCIe base 5.0 sections 4.2.10-11), Gen5 jitter measurement (PCIe base 5.0 sections 4.2.12).
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGAs and SoC FPGAs I-Series, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language VHDL

RTL with options for both encrypted as well as complete source code.

Easy GUI/Script-based environment to program IP with different configurations.

Example design with simulation test scripts.

Synthesizable example design with required constraint files.

Detailed user and functional programming guide.

Ordering Information

sales@logic-fruit.com

from Direct

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