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100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. 

Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
  • 128-bit wide bi-directional data paths with streaming interfaces
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • DPDK Stream interface (optional)
  • Corundum NIC integration with performance DMA and PCIe (optional)
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Offering Brief

Offering Brief

Device Family Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Stratix® 10 GX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® 10 GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Modular and application-specific 100G TCP/IP cores, and example design projects

Single-Project or Multi-Project Use for ASIC or FPGA

Delivered as encrypted netlists or RTL

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments