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NVMe Controller (Silicon Proven IP for Altera Devices)

Mobiveil Inc.

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Highly configurable NVMe (UNEX) controller IP for client and enterprise SSDs, optimized for link/throughput utilization, latency, reliability, power, and silicon footprint. Supports multipath I/O, namespace sharing, optional admin/NVM command sets, E2E protection, and rich DMA/queue configurability. UNEX is a technology-independent, system-validated NVMe controller offered in three interface “flavors” (native, AXI4-ST/AXI streaming, and AXI memory interface variants) to pair with Intel PCIe HIP or third-party PCIe controllers. It implements NVMe 2.1 features including optional admin/NVM command sets, Zoned Namespace (ZNS), Key-Value, Copy/Lock, multipath I/O & namespace sharing, and E2E protection (16/32/64b). Internally, it scales via configurable data paths (128/256/512-bit), queue count/depth, and multiple DMA engines. Deliverables include synthesizable Verilog RTL, UVM testbench, protocol checkers, bus watchers, perf monitors, synthesis shell, and an N...

Highly configurable NVMe (UNEX) controller IP for client and enterprise SSDs, optimized for link/throughput utilization, latency, reliability, power, and silicon footprint. Supports multipath I/O, namespace sharing, optional admin/NVM command sets, E2E protection, and rich DMA/queue configurability. UNEX is a technology-independent, system-validated NVMe controller offered in three interface “flavors” (native, AXI4-ST/AXI streaming, and AXI memory interface variants) to pair with Intel PCIe HIP or third-party PCIe controllers. It implements NVMe 2.1 features including optional admin/NVM command sets, Zoned Namespace (ZNS), Key-Value, Copy/Lock, multipath I/O & namespace sharing, and E2E protection (16/32/64b). Internally, it scales via configurable data paths (128/256/512-bit), queue count/depth, and multiple DMA engines. Deliverables include synthesizable Verilog RTL, UVM testbench, protocol checkers, bus watchers, perf monitors, synthesis shell, and an NVMe device FW stack.

Key Features

  • Compliance with NVM Express 2.1 specification
  • AXI4-ST/AXI interface support towards the PCIe interface.
  • AXI4 interface support towards the memory subsystem.
  • Configurable internal data path width of 128, 256, or 512 bits.
  • Host memory page size support up to 128 MB.
  • Round robin or weighted round robin arbitration with urgent priority mechanism.
  • Configurable number of I/O queues and queue depth.
  • Support for all optional admin and NVM commands.
  • Multipath I/O and namespace sharing with multiport configuration support.
  • End-to-end data protection with 16-bit, 32-bit, and 64-bit coverage.
  • Zoned Namespace and Key Value command set support.
  • Additional Copy and Lock command support for enhanced functionality.
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Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, eASIC™ N3X Devices, eASIC™ N3XS Devices, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Development Language Encrypted Verilog, Verilog

RTL Code

UVM based test bench and behavioral models

Test cases

Protocol checkers, bus watchers and performance monitors

Configurable synthesis shell

NVM Device FW Stack

Design Datasheet

Verification Guide

Synthesis Guide

NVM Device FW API User Guide

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments