10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency.

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Key Features

Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
128-bit wide bi-directional data paths with streaming interfaces
Multiple, parallel TCP engines for scalable processing
DPDK Stream interface (optional)
DPDK Stream interface (optional)
Corundum NIC integration with performance DMA and PCIe (optional)

Offering Brief

Device Family	Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	25.1.1
Development Language	Encrypted Verilog, Encrypted VHDL, Verilog, VHDL