PCIe to SRIO Bridge Controller (FPGA IP for Altera Devices)

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Mobiveil Inc.

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High-performance protocol bridge IP connecting x4 PCIe Gen3 ↔ x4 SRIO Gen3, with configurable x4/x2/x1 ports, BRC3 10.3125 Gbaud support, up to 8 DMA channels (2 in Light RAB), deep per-channel buffering, and robust error handling (AER/IER). Technology-independent, system-validated bridge that sustains line-rate transfers (≥64-byte SRIO packets) between PCIe and SRIO. Features include x4/x2/x1 on both PCIe and SRIO, BRC1/BRC2/BRC3 data rates (1.25→10.3125 Gbaud), 8 KB packet buffering per DMA/messaging channel, MSI-X (70 vectors), ECRC, AER/IER, lane reversal and polarity inversion on PCIe, and hot-insert/extract on SRIO. Addressing supports RIO 34/50/66-bit and AXI 32/38/64-bit; clocking at 100/125/156.25 MHz for both endpoints. Delivered with synthesizable Verilog RTL, comprehensive verification environment, and design/user/synthesis guides.

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Key Features

Bridges x4 PCIe Gen3 to x4 SRIO Gen3, with port scalability to x4, x2, or x1 configurations.
PCIe/SRIO operation at BRC1 (Gen1): 1.25, 2.5, 3.125, 5 Gbaud; BRC2 (Gen2): 6.25 Gbaud; BRC3 (Gen3): 10.3125 Gbaud.
Hardware-configurable up to 8 DMA channels (Light RAB = 2 channels), with 8 KB buffering per DMA and per messaging channel.
PCIe I/O buffers up to 12 KB, SRIO ingress buffer 8 KB, ensuring sustained throughput.
Works with 100 MHz, 125 MHz, and 156.25 MHz reference clocks on both PCIe and SRIO endpoints.
Implements Advanced Error Reporting (AER), Internal Error Reporting (IER), and End-to-End CRC (ECRC) for data integrity.
Supports automatic polarity inversion and lane reversal for simplified board routing.
RIO addressing: 34-bit, 50-bit, 66-bit; AXI addressing: 32-bit, 38-bit, 64-bit.
Maximum packet size 256 B, maximum read request size 4 KB, up to 32 concurrent transactions, MSI-X with 70 vectors, and PCIe-compliant power management.
Supports multiple SRIO transaction types: NRead, SWrite, NWrite_R, Port Write, Doorbell, with hot-insert/extract capability.
Utilizes an APB (pBus) interface for programming Control and Status Registers.
Delivers line-rate performance for SRIO packets ≥ 64 bytes, maximizing interconnect efficiency.

Offering Brief

Device Family	Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog