PCIe Gen5/6 Switch (FPGA IP for Altera Devices)

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Mobiveil Inc.

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FPGA PCIe® multi-port switch IP built on PCIe hard IP blocks with x16 upstream / up to x8 per downstream, non-blocking fabric, cut-through & store-and-forward modes, and full PCIe 5.0 compliance (backward-compatible to Gen4/3/2/1). Solution stitches the FPGA’s PCIe HIPs (upstream + multiple downstream ports) with a Mobiveil switch fabric to create a configurable transparent/non-transparent PCIe switch. Supports single-port & multi-port configs, flexible upstream/downstream lane widths, 32/64/128/256/512-bit datapaths, flow control in both directions, advanced error reporting, power management (L0s/L1/L1 sub-states), and per-port feature sets. Includes AMBA master/slave option for app logic, parallel address decoding at each ingress, arbitration (round-robin / strict-priority with starvation detection), and full collateral (RTL, UVM TB, protocol checkers, perf monitors, synth guides). Built to PCIe 5.0 (32 GT/s); roadmap aligns with Gen6 controller/swit...

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Key Features

Multi-port FPGA PCIe switch using embedded PCIe hard IP blocks, available on Xilinx FPGAs.
Upstream up to x16 lanes, downstream up to x8 lanes, with programmable link widths and reconfiguration support.
Flexible datapaths (32/64/128/256/512-bit) and per-port unique feature sets to match diverse application needs.
Cut-through and store-and-forward (SNF) – in a non-blocking, low-latency architecture for high link utilization.
PCIe 5.0 compliant (32 GT/s per lane) with full backward compatibility to PCIe 4.0, 3.1, 2.0, and 1.1, and compliant with PCI-to-PCI Bridge Architecture spec.
Advanced traffic handling – PCIe ordering rules, bidirectional flow control, and arbitration via round-robin or strict-priority with starvation detection.
Robust error handling – Advanced Error Reporting (AER), unsupported request/unexpected completion management for upstream/downstream traffic.
Power management support – PCI-PM, ASPM (L0s, L1, L1 sub-states), and sub-state configurations for internal and downstream devices.
Parallel address decoding at each ingress port with type-1/type-0 conversion for configuration transactions.
AMBA Master/Slave interfaces available for direct integration with application logic.
High-reliability design – ensures ordering compliance, link re-configuration, and consistent performance under heavy load.
Configurable port arbitration and programmable link width enable optimal adaptation to changing system requirements.

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	No
Demo	No
Compliance	No
Hardware Platforms Supported	Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog