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PTP Ordinary Clock (IEEE1588 – Precision Time Protocol)

NetTimeLogic GmbH

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NetTimeLogic’s PTP Ordinary Clock (OC) is a full hardware (FPGA) only implementation of an Ordinary Clock according to IEEE1588-2019 (PTP). The whole protocol handling, algorithms and calculations are implemented in the core, no CPU is required which allows running PTP synchronization completely independent and standalone from the user application. The Ordinary Clock can act as Master and Slave based on the Best Master Clock algorithm (BMCA) and supports the following PTP Profiles: Default Profile, Power Profile, Utility Profile, TSN Profile (802.1AS) and ITU Profiles (ITU-T-G82651/G82751/G82752)

Key Features

  • PTP Ordinary Clock according to IEEE1588-2019/2008
  • Support for Default Profile: Layer 2 (Ethernet) and Layer 3 (IP) support
  • Support for Power Profile: C37.238-2011 and C37.238-2017 including VLAN support
  • Support for Utility Profile: including HSR and PRP tag handling
  • Support for IEEE802.1AS-REV: including IEEE802.1CB tag handling
  • Support for ITU Profiles : ITUG82651, ITUG82751, ITUG82752, up to 4096 Unicast Slaves at 128 frames/s
  • One Step and Two Step support
  • Peer to Peer (P2P) and End to End (E2E) delay measuremen
  • Master and Slave support
  • AXI4 Light register set or static configuration
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Cyclone® IV E FPGA, Stratix® 10 AX SoC FPGA
Offering Status Production
Demo No
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance No
Intertop ISPCS, IIC
Latest Quartus Version Supported 25.1.0
OS Support Not required
Development Language VHDL

Source Code

Testbench

Documentation

Reference Design

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