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DE1-SoC Board

Terasic Inc.

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The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility.

Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone.

The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more. The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later ( 64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC ).

The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility.

Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone.

The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more. The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later ( 64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC ).

Key Features

  • 64MB SDRAM on FPGA and 1GB DDR3 SDRAM on HPS
  • Two GPIO Headers
  • 24-bit VGA DAC and 24-bit Audio Codec
  • TV Decoder (NTSC/PAL/SECAM) and TV-in connector
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Offering Brief

Offering Brief

Device Family Cyclone® V SE SoC FPGA
Offering Status Production
Device OPN(s) on Board 5CSEMA5F31C6N
Form Factor 166*130 mm
Power 12V DC Power Supply
Interfaces InfraRed
Ethernet
USB
onboard UB2
GPIO
SDRAM
DDR3
TV-in
Memory 64MB SDRAM on FPGA and 1GB DDR3 SDRAM on HPS; EPCS128
Connectors USB; Ethernet; PS/2; GPIO Headers; ADC Input Header; LTC connector
Switches & LEDs 10 User switches (FPGA x10) and 11 User LEDs (FPGA x10 ; HPS x 1)
Latest Quartus Version Supported 20.1.1
Prerequisites N/A
Languages English
Target Audience Academia
Hands On Lab True

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Reference Design

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