Terasic Cyclone® V SoC Development Kit with HSMC Connector (DE10-Standard)

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Terasic Inc.

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Built around the Altera SoC FPGA, the DE10-Standard Development Kit combines a dual-core ARM Cortex-A9 hard processor system (HPS) with industry-leading programmable logic, connected through a high-bandwidth interconnect backbone. The HPS integrates processors, peripherals, and memory interfaces, enabling seamless collaboration between hardware and software. The board includes high-speed DDR3 memory, video and audio interfaces, Ethernet networking, and other rich hardware resources, making it an ideal platform for advanced embedded systems, multimedia processing, and networking applications.

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Key Features

Dual-Core ARM Cortex‑A9 Hard Processor System (HPS)
Memory and Configuration
Rich Multimedia & I/O Interfaces
Expansion & Analog Features
User Controls & Indicators

Offering Brief

Device Family	Cyclone® V SX SoC FPGA
Offering Status	Production
Form Factor	166*130 mm
Power	12V
Interfaces	VGA, 128x64 Dots LCD, 24-bit CODEC, USB to UART, Gigabit Ethernet, USB 2.0 Host x2, PS/2, IR
Memory	EPCS128, 64MB SDRAM, 1GB DDR3, MicroSD Card Socket
Connectors	40-pin expansion headers, One 10-pin Analog input, LTC 2x7, HSMC
Switches & LEDs	Reset Button, Power Button, Power LED, User-Programmable LEDs, Switch and Button
Latest Quartus Version Supported	16.1.1