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XIP2113B: Balanced IP core for ChaCha20-Poly1305 Authenticated Encryption

Xiphera Ltd.

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ChaCha20-Poly1305 balanced IP core deliver both encryption and authentication by combining the high-speed ChaCha20 stream cipher with the Poly1305 authenticator. The ChaCha20-Poly1305 IP cores can be used in an AEAD scheme in multiple protocols, including TLS 1.3.

Key Features

  • Moderate resource requirements: The entire XIP2113B requires 5052 Adaptive Lookup Modules (ALMs) (Intel® Arria® 10 GX).
  • Performance: XIP2113B achieves a throughput in the tens of Gbps range2, for example 6.96+ Gbps in Xilinx® Zynq® MPSoC. Even higher throughputs can be achieved with parallel instantiations of XIP2113B.
  • High Throughput with Short Latency: XIP2113B offers very high throughput for a single stream of data as it is capable to process one 16-byte block per clock cycle after certain initial latency. The length of the initial latency depends on the length of the message and XIP2113B has been carefully optimized to minimize this initial latency.
  • Constant Latency: The execution time of XIP2113B is independent of the key values and message contents (apart from the message length), and consequently provides full protection against timing-based side-channel attacks.
  • Standard Compliance: XIP2113B is fully compliant with RFC 8439 “ChaCha20 and Poly1305 for IETF Protocols” [3].
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted VHDL, VHDL

Encrypted RTL or source code

Sample synthesis scripts

Optional netlist

Instantiation file

Comprehensive simulation test bench, scripts & guide

Detailed datasheet and integration guide

Ordering Information

Market Segment and Sub-Segments