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XIP4001C: Curve25519 Key Exchange IP Core

Xiphera Ltd.

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Curve25519 compact IP core offers public-key exchange. The IP core is optimised for both performance and resource efficiency in both FPGA and ASIC implementations, offering versatile functionality across various cryptographic protocols.

Key Features

  • Minimal Resource Requirements: The entire XIP4001C requires less than 1k Logic Elements and uses only 1-2 multipliers/DSP Blocks2 and one internal memory block in a typical FPGA implementation.
  • Constant Latency: The execution time of XIP4001C is independent of the key value, and consequently provides protection against timing-based side-channel attacks.
  • Performance: Despite its small size, XIP4001C can support more than 100 key exchange operations per second.
  • Standard Compliance: XIP4001C is compliant with RFC7748 [1], and can be used as a part of many public-key protocols including IKEv2 (RFC 8031) [3] and TLS 1.3 (RFC 8446) [4].
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted VHDL, VHDL

Encrypted RTL or source code

Optional netlist

Sample synthesis scripts

Instantiation file

Comprehensive simulation test bench, scripts & guide

Detailed datasheet and integration guide

Ordering Information

Market Segment and Sub-Segments