CoaXPress-over-Fiber Bridge Device IP core

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Sensor to Image GmbH

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The CoaXPress-over-Fiber Device Bridge IP Core allows to connect a CoaXPress Device IP Core to an nGMII (10/25 Gbps Media Independent Interface) bus inside an FPGA. nGMII, as defined in IEEE Std 802.3 Clause 46, is the main access to the 10/25G Ethernet physical layer. Delivered as working reference design (when licensed with S2I CoaXPress Device IP Core) and extensive simulation testbench.

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Key Features

Extension for CoaXPress 2.1 compliant IP for camera applications
Support of multiple connections
Speed support up to 100Gbps

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GX FPGA, Cyclone® 10 GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	Yes
Intertop	JIIA Compliance Test
Latest Quartus Version Supported	24.3.1
Development Language	VHDL, Encrypted VHDL

Reference Design for Altera Evaluation Kit

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