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1G UDP Offloading Engine (UDP1G-IP)

DesignGateway Co., Ltd.

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Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack that eliminates the need for external CPUs. This architecture ensures real-time data communication with consistent performance, making it well-suited for systems where software-based stacks fall short, such as broadcast, online gaming, industrial automation, and aerospace & defense. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, enabling fast and efficient system integration. Proven in mission-critical deployments, Design Gateway's UDP-IP cores deliver a scalable and dependable solution for high-speed networking. By offloading the UDP/IP stack entirely to hardware, they help reduce CPU workload, minimize latency, and enhance syst...

Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack that eliminates the need for external CPUs. This architecture ensures real-time data communication with consistent performance, making it well-suited for systems where software-based stacks fall short, such as broadcast, online gaming, industrial automation, and aerospace & defense. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, enabling fast and efficient system integration. Proven in mission-critical deployments, Design Gateway's UDP-IP cores deliver a scalable and dependable solution for high-speed networking. By offloading the UDP/IP stack entirely to hardware, they help reduce CPU workload, minimize latency, and enhance system reliability across a wide range of demanding applications.

Key Features

  • Fully hardware-based UDP/IP stack for real-time, low-latency communication
  • IPv4 support with full-duplex transfer using separate ports for each direction
  • Configurable buffer sizes (2 KB to 64 KB) and simple FIFO-based data interface
  • Supports multicast, broadcast, and IP fragmentation for versatile networking
  • Offloads CPU workload, enhancing system performance and reliability
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Arria® 10 GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo Yes
Compliance No
Latest Quartus Version Supported 23.1.0
Development Language Encrypted VHDL

Encrypted IP core

Reference Designs Quartus Project

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