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10M/100M/1G/10G/25G High capacity Ethernet TSN Switch

Comcores ApS

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The Comcores 10M/100M/1G/10G/25G/100G Ethernet TSN Switch IP is a high-performance, silicon-agnostic switching solution designed for advanced, time-critical Ethernet applications. Supporting up to 800 Gbps of switching capacity, the IP integrates rich QoS capabilities, detailed statistics, and a comprehensive suite of Time Sensitive Networking (TSN) features, including frame preemption, time-aware and credit-based shaping, per-stream filtering and policing, and frame replication and elimination for reliability. With support for up to eight queues per port, VLAN 802.1Q, multicast and broadcast handling, IGMP snooping, Rapid Spanning Tree Protocol, DSA, and IEEE 1588 transparent and boundary clocks, the switch enables deterministic, low-latency operation across a wide range of speeds. Each port provides a native PHY interface, configurable at compile time from 10 Mbps to 100 Gbps, while TSN features can be selectively enabled to match system requirements. Delive...

The Comcores 10M/100M/1G/10G/25G/100G Ethernet TSN Switch IP is a high-performance, silicon-agnostic switching solution designed for advanced, time-critical Ethernet applications. Supporting up to 800 Gbps of switching capacity, the IP integrates rich QoS capabilities, detailed statistics, and a comprehensive suite of Time Sensitive Networking (TSN) features, including frame preemption, time-aware and credit-based shaping, per-stream filtering and policing, and frame replication and elimination for reliability. With support for up to eight queues per port, VLAN 802.1Q, multicast and broadcast handling, IGMP snooping, Rapid Spanning Tree Protocol, DSA, and IEEE 1588 transparent and boundary clocks, the switch enables deterministic, low-latency operation across a wide range of speeds. Each port provides a native PHY interface, configurable at compile time from 10 Mbps to 100 Gbps, while TSN features can be selectively enabled to match system requirements. Delivered with solid documentation, a drop-in default configuration, and supporting software, the Verilog-based IP is optimized for both FPGA and ASIC implementations, making it a flexible and scalable choice for high-speed, time-sensitive networking designs.

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Key Features

  • 10M, 100M, 1G, 10G, 25G and 100G ports configurable at compile time
  • Up to 800Gbps switching capacity
  • Parallel Lookup Engines enable high packet processing rate
  • CPU packet port up to 25 Gbps
  • QoS features including classification, queuing and scheduling
  • Supports VLAN, Supports IGMP snooping
  • Supports Rapid Spanning Tree Protocol, Supports DSA
  • IEEE 1588 functionality including both transparent and boundary clock
  • Frame Preemption, Time Aware Shaping, Credit Based Shaping, Per-Stream
  • Filtering and Policing, Frame Replication and Elimination for Reliability
  • TSN features can be enabled/disabled independently
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Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Solid documentation, including User Manual and Release Note

Simulation Environment, including Simple Testbed, Test case and Test Script

Programming Register Specification

Timing Constraints in Synopsys SDC format

Access to support system and direct support from Comcores Engineers

Synopsys SGDC Files (optional)

Synopsys Lint, CDC and Waivers (optional)

Ordering Information

CM_ETHSWI_07_B_F

from Directly from Comcores

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