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40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

Key Features

  • Highly modular UDP/IP stack implementation in synthesizable HDL
  • Network Interface Card functionality with Bypass (optional)
  • DPDK Stream interface (optional)
  • Corundum NIC integration with performance DMA and PCIe (optional)
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® III FPGA, Stratix® IV GX FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Modular and application-specific 40G UDP IP Cores, and example design projects

Single-Project or Multi-Project Use for ASIC or FPGA

Delivered as encrypted netlists or RTL

Ordering Information

Market Segment and Sub-Segments