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Lossless and Lossy JPEG 2000 Encoder

Alma Technologies S.A.

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The JPEG2K-E core from Alma Technologies is a still image and video encoder that implements Part 1 of the JPEG 2000 standard. It offers up to 16-bit per component Numerically Lossless or Lossy compression, including advanced - high-quality and extremely accurate - rate control functionality. The JPEG2K-E can also optionally include support for single-component Multiple Quality Layers encoding in LRCP progression order. It is available for Altera FPGA and SoC based designs.

The JPEG 2000 compression standard offers an advanced quality and feature set, lending itself to a wide range of uses from digital cameras through to space imaging and other key sectors. Full compliance to the ISO/IEC 15444-1 JPEG 2000 standard makes the JPEG2K-E core ideal for interoperable systems and devices.

Key Features

  • Up to 65,535 x 65,535 image resolution
  • Up to 16,384 x 16,384 tile resolution
  • 1, 2, 3 and 4 component images
  • Up to 16-bit per component
  • 4:4:4, 4:2:2, 4:1:1 and 4:2:0 sampling formats
  • Numerically lossless or lossy compression
  • Advanced rate control engine
  • Single or multiple quality layers encoding
  • CPRL or LRCP (single component only) progression order
  • Error resilient encoding features
  • Standard compliant code stream (JPC) or file (JP2) output
  • No host CPU assisted, standalone operation
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language VHDL

Pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist

Self-checking testbench environment sources, including sample BAM generated test cases

Sample Simulation and Place & Route scripts

Ordering Information

Market Segment and Sub-Segments