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Lossless and Lossy CCSDS 122.0-B-1 Encoder

Alma Technologies S.A.

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The CCSDS-122-E encoder IP core from Alma Technologies is a complete and self-contained implementation of the CCSDS 122.0-B-1 image data compression standard. It offers numerically lossless or Lossy image data compression with up to 16-bit pixel dynamic range. The encoder accepts the uncompressed image data in standard raster-scan pixel order and outputs standalone and fully compliant CCSDS 122.0-B-1 byte-stream format. The CCSDS-122-E is designed for enabling high-rate data compression with low silicon resource usage and without needing an external memory device for its operation. It is available for Altera FPGA and SoC based designs.

The CCSDS 122.0-B-1 standard was developed to balance between compression performance and complexity. Similar to JPEG 2000, it utilizes a two-dimensional Discrete Wavelet Transform (DWT) for image data decorrelation. CCSDS 122.0-B-1 uses a 9/7 integer DWT for the lossless compression, while a 9/7 float DWT is also specifie...

The CCSDS-122-E encoder IP core from Alma Technologies is a complete and self-contained implementation of the CCSDS 122.0-B-1 image data compression standard. It offers numerically lossless or Lossy image data compression with up to 16-bit pixel dynamic range. The encoder accepts the uncompressed image data in standard raster-scan pixel order and outputs standalone and fully compliant CCSDS 122.0-B-1 byte-stream format. The CCSDS-122-E is designed for enabling high-rate data compression with low silicon resource usage and without needing an external memory device for its operation. It is available for Altera FPGA and SoC based designs.

The CCSDS 122.0-B-1 standard was developed to balance between compression performance and complexity. Similar to JPEG 2000, it utilizes a two-dimensional Discrete Wavelet Transform (DWT) for image data decorrelation. CCSDS 122.0-B-1 uses a 9/7 integer DWT for the lossless compression, while a 9/7 float DWT is also specified for improved lossy compression efficiency, especially at low bit-rates. Both DWT options are available by the CCSDS-122-E core. For complete control by the application of the lossy compression ratio, the CCSDS-122-E includes also the optional rate control functionality that is provisioned by the standard.

The CCSDS-122-E is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. It is a complete and autonomous encoder, not needing any host system CPU or GPU support for its operation. Being carefully designed and rigorously verified, the CCSDS-122-E is a reliable and easy-to-use and integrate IP core.

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Key Features

  • Full compliance to the CCSDS 122.0-B-1 specification
  • Numerically lossless or lossy compression
  • Up to 16 bits pixel dynamic range
  • Both integer and float 9/7 DWT filters
  • Integrated rate control
  • Operation without external memory
  • CPU/GPU-less, complete and standalone implementation
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Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language VHDL

Pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist

Self-checking testbench environment sources, including sample BAM generated test cases

Sample Simulation and Place & Route scripts

Ordering Information

CCSDS-122-E

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Documentation & Resources

design hub icon CCSDS-122-E designer's reference manual

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