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Creonic DVB-S2 BCH and LDPC Decoder and Encoder

Creonic GmbH

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The Creonic DVB-S2 LDPC / BCH Decoder and Encoder IP cores perform forward error correction as defined within the standard. Furthermore, the Encoder includes additional signal processing before and after encoding, i.e., interleaving and scrambling. The Decoder includes additional signal processing before and after forward error correction (soft-decision demapping, deinterleaving, descrambling).

Key Features

  • Compliant with ETSI EN 302 307 V1.2.1 (2009-08) (DVB-S2)
  • Supports ACM, CCM, and VCM modes
  • Support for decoding of BBFrames
  • Support for short and long blocks (16,200 bits and 64,800 bits)
  • Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, and 32-APSK)
  • Support for all interleaving schemes of all modulation schemes
  • Support for all LDPC and BCH codes as defined by the standard
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 22.4.0
Development Language C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model​

Ordering Information

Documentation & Resources

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