Creonic DVB-S2X Multi-Carrier Demodulator

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The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel. The demodulator expects quantized real samples in an intermediate frequency (IF) from an analog-digital-converter (ADC). It separates the carriers with FFT/IFFT processing and then performs all further demodulation steps in a time-multiplexed way. It recovers timing, frequency and phase of the complex mapped symbols for each carrier individually. In addition, the core handles PL frame recovery and PL deframing.

The demodulator can work with the Creonic DVB-S2X LDPC/BCH Decoder IP core by inserting a glue logic between the cores. The glue logic can be provided upon customer request.

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Key Features

Supports CCM, ACM and VCM
Supports roll-off factors 5%, 10%, 15%, 20%, 25% to 35%
Support for short and normal blocks (16,200 bits and 64,800 bits) with pilots only
Support for QPSK to 256-APSK
Optional VLSNR support
Output of XFECFRAMEs for further processing by the Creonic DVB-S2X LDPC/BCH decoder

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	22.4.0
Development Language	C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

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