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DI2CMS - I2C Bus Interface - Master/Slave

DCD-SEMI

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The DI2CMS is a flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for both SMBus (System Management Bus) and PMBus (Power Management Bus) protocols. Designed to meet the latest I2C v3.0 specification, the DI2CMS core is composed of two primary modules: DI2CM (Master) and DI2CS (Slave), enabling operation as either a master or slave device on the bus.

The core supports advanced I2C features such as multi-master arbitration, clock synchronization, and controller clock stretching, making it suitable for complex, multi-master environments. Transmission speeds are configurable up to 3.4 Mb/s, covering all standard I2C modes – Normal (100 kHz), Fast (400 kHz), Fast-plus (1 MHz), and High-Speed (3.4 MHz) – as well as all predefined SMBus and PMBus clock frequencies.

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Key Features

  • Conforms to the I2C v3.0 specification
  • Support for SMBus and PMBus protocols
  • Both master and slave transmitter/receiver modes
  • Multi-master support with bus arbitration
  • Controller clock stretching and synchronization
  • Clock stretching warning signal
  • Clock low timeout detection
  • User-configurable clock and data timings via: Sythesis parameters, Dynamic registers reconfiguration
  • 7 and 10-bit addressing in master mode
  • SMBus Alert and PMBus control line support
  • Up to 8 target addresses in slave mode
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Verilog

HDL Source Code

Testbench environment - automatic simulation macros, tests with reference responses

Synthesis scripts

Technical documentation

12 months of technical support

Ordering Information

DI2CMS

from Direct

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Documentation & Resources

design hub icon Datasheet

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