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DSENT - Cutting-Edge SENT Protocol IP Core for Automotive Communication

DCD-SEMI

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The DSENT, a hardware implementation of the Single Edge Nibble Transmission (SENT) protocol controller. Designed to comply with the SAE-J2716 standard, DSENT delivers a robust, low-cost solution for reliable data communication between automotive sensors and central units such as Engine Control Units (ECUs).

The SENT protocol is a single-wire communication system optimized for transmitting signal values through precise time measurement between two falling signal edges. DSENT offers hardware-based efficiency, enabling seamless data exchange either as a transmitter in sensors or a receiver in central units.

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Key Features

  • Versatility in Communication: Supports Fast and Slow Channel transmission or reception.
  • Automatic Data Rate Synchronization: Maintains stable data exchange despite variations in clock accuracy.
  • Customizable Data Length: Configurable from 1 to 6 nibbles for enhanced flexibility.
  • Advanced Error Detection: Features optional automatic CRC error detection and Frame Error.
  • Hardware CRC calculation in Transmit mode.
  • Pause Pulse Support: Includes optional Pause Pulse Period functionality for operational efficiency.
  • Master Trigger Pulse Support: Enables communication with up to four sensors over a single wire.
  • Technology Independence: Fully synthesizable and implementable across various process technologies.
  • A 56-tick calibration/synchronization pulse.
  • Status and communication nibbles spanning 12 to 27 ticks.
  • Up to six data nibbles of similar durations.
  • A CRC checksum nibble for data validation.
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Verilog

HDL Source Code

Testbench environment - automatic simulation macros, tests with reference responses

Synthesis scripts

Technical documentation

12 months of technical support

Ordering Information

DSENT

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Documentation & Resources

design hub icon Datasheet

Market Segment and Sub-Segments

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Transportation

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Transportation

Automotive (Passenger Vehicles)

Charging Infrastructure

Non-Automotive Transportation

Transportation Infrastructure (non-charging)

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