IRIG Slave

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NetTimeLogic GmbH

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NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an IRIG-B004, B005, B006 and B007 or IRIG-G006Master. The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application.

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Key Features

IRIG Slave Clock
Supports IRIG-B006/IRIG-G006 format (compatible with B004, B005, B006 and B007 IRIG-B Masters)
Optional support Control Bits for IRIG-B000/B001/B004/B005
Optional AM decoding and amplitude demodulation for IRIG-B120 - B127 or IRIG-G146 (requires an external ADC)
IRIG decoding and time format conversion
IRIG supervision
Input delay compensation
Cable delay compensation
Additional seconds correction to convert between UTC and TAI time (or any other time base)
AXI4 Light register set or static configuration

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Cyclone® IV E FPGA, Stratix® 10 AX SoC FPGA
Offering Status	Production
Demo	No
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Compliance	No
Intertop	ISPCS, IIC
Latest Quartus Version Supported	25.1.0
Development Language	VHDL