This course provides all necessary know-how for hardware engineers that would like to design with Agilex™ 5 SoC FPGA. The training starts by introducing the Agilex™ 5 FPGAs architecture (I/O, DSP, RAM, PLLs, etc.), it’s 2nd generation Hyperflex architecture, and the Quartus® Prime Design Software for Agilex™ 5.
The training continues by teaching how to implement high-speed external memory interfaces, high speed serial interfaces, PCIe and Ethernet (with TSN).
Next, the Hard Processor Subsystem (HPS) is covered with Cortex-A76 and Cortex-A55, along with their peripherals, NoC architecture, design considerations and debug capabilities.
The training ends with the Agilex™ 5 security features and functional safety.
An optional extension available is the FPGA AI suite for Agilex™ 5 and the design flow for AI.