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Gen5 AGILEX 7 R-Tile NVMe Host IP

Logic Design Solutions

Member

The LDS NVME HOST IP has been done for beginners and experts in NVMe to drive NVMe PCIe SSD. The LDS NVME HOST IP provides two interfaces: One CPU interface for long sequential recording or reading. One FIFO interface for I/O intensive data transfer. The register file interface simplifies the management of the IP for CPU interface or State Machine interface using Avalon bus: PCIe RP and EP register configuration is done automatically. NVMe register configuration is done automatically. Able to manage 8 Name Spaces. Able to manage until 16 IO Queue to able Multi-users. Each IO Queue is independent. Able to manage 512Bytes or 4096Bytes sector size. Able to run nearly all Admin commands in parallel of IO Queue. Some IO commands already pre-defined to ease use of the IP. Configurable IO Queue buffer size to fit user memory requirement: 32KB, 64KB, 128KB, 256KB, 512KB or 1024KB. Able to read all PCIe RP and EP registers. Able to stop current commands. ...

The LDS NVME HOST IP has been done for beginners and experts in NVMe to drive NVMe PCIe SSD. The LDS NVME HOST IP provides two interfaces: One CPU interface for long sequential recording or reading. One FIFO interface for I/O intensive data transfer. The register file interface simplifies the management of the IP for CPU interface or State Machine interface using Avalon bus: PCIe RP and EP register configuration is done automatically. NVMe register configuration is done automatically. Able to manage 8 Name Spaces. Able to manage until 16 IO Queue to able Multi-users. Each IO Queue is independent. Able to manage 512Bytes or 4096Bytes sector size. Able to run nearly all Admin commands in parallel of IO Queue. Some IO commands already pre-defined to ease use of the IP. Configurable IO Queue buffer size to fit user memory requirement: 32KB, 64KB, 128KB, 256KB, 512KB or 1024KB. Able to read all PCIe RP and EP registers. Able to stop current commands. Able to manage low data rate in reading. Easy connection to embedded Root Port R-Tile PCIe IP through Avalon bus. FAT32 / EXFAT available as an option.

Key Features

  • Flexible IP
  • CPU and FIFO Interface
  • Multi-Users
  • IO Queue buffer size : 32KB, 64KB, 128KB, 256KB, 512KB or 1024KB
  • Able to stop current command
  • Able to manage low data rate in reading
  • Easy connection to embedded Root Port R-Tile PCIe IP through Avalon bus
  • FAT32 / EXFAT available as an option
  • RAID0 managed automatically
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGAs and SoC FPGAs I-Series
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available Yes
Demo Yes
Compliance No
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 25.1.1
Development Language VHDL

Complete Quartus Project

IP Data Sheet

Demo Data Sheet

Several Example Design

Source or Encrypted VHDL Code

Ordering Information

Market Segment and Sub-Segments