Lossless JPEG-LS Encoder

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Alma Technologies S.A.

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The JPEGLS-E core from Alma Technologies is an ISO/IEC 14495-1 compliant JPEG-LS encoder that offers a very compact, efficient and high-performance solution for up to 16-bit per component numerically lossless image and video data compression. The JPEG-LS standard offers the JPEG 2000 lossless compression efficiency advantage in much more compact silicon footprint and without requiring access to an external memory device. The JPEGLS-E is available for Altera FPGA and SoC based designs.

JPEG-LS was developed to provide a low complexity lossless image compression standard with better compression potentials than Lossless JPEG. The algorithm at the core of JPEG-LS is LOCO-I (Low Complexity-Lossless Compression for Images). It uses a non-linear predictive scheme with rudimentary edge detecting capability, based on the four nearest -causal- neighbours (left, upper left, upper and upper right) and an entropy encoder which uses adaptively selective Golomb-type codes. The low complexity scheme of JPEG-LS is based on the assumption that prediction residuals follow a two-sided geometric distribution and the fact that Golomb-codes are optimal for geometric distributions, thus the modeling and coding units are matching.

The JPEGLS-E core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEGLS-E is a reliable and easy-to-use and integrate IP.

The JPEGLS-E is also available in a configuration that adds support for the JPEG-LS NEAR-Lossless encoding mode. The NEAR-Lossless configuration offers higher compression at user defined maximum allowed reconstructed data error, but runs much slower due to a different data-path architecture which has to include feedback loops that cannot be pipelined while maintaining the single clock cycle per input sample processing rate.

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Key Features

Up to 64K x 64K image resolution
Single-component, 4:4:4, 4:2:2, 4:1:1 and 4:2:0 chroma sampling formats
Up to 16-bit per component programmable sample depth
Run-length coding
Programmable point transform
Programmable local gradient thresholds
Programmable context parameters reset threshold value
Complete, standalone JPEG-LS stream output
Single clock cycle per sample encoding throughput
CPU-less, standalone operation

Offering Brief

Device Family	Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
Development Language	Verilog, VHDL