NVMe Streamer 4.0: NVMe IP PCIe Gen4 High-speed Data Streaming - MLE FPGA Design

Overview Key Features Offering Brief What's Included Ordering Information Markets

NVMe Streamer is a fully integrated and pre-validated subsystem stack operating the NVMe protocol fully in Programmable Logic (PL) with no software running, keeping the Processing System (PS) out of this performance path.

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Key Features

Provides one or more NVMe / PCIe host ports for NVMe SSD connectivity
Full Acceleration means “CPU-less” operation
Fully integrated and tested NVMe Host Controller IP Core
PCIe Enumeration, NVMe Initialization & Identify, Queue Management
Control & Status interface for IO commands and drive administration
Approx. 50k LUTs and 170 BRAM tiles
Compatible with PCIe Gen 1 (2.5 GT/sec), Gen 2 (5 GT/sec), Gen 3 (8 GT/sec), Gen 4 (16 GT/sec) speeds
Scalable to PCIe x1, x2, x4, x8 lane

Offering Brief

Device Family	Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA
Offering Status	Development
Integrated Testbench	No
Evaluation License	No
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	25.1.1
Development Language	Verilog, VHDL