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Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

Key Features

  • Platform and device vendor independent core
  • Supports 10G or 25G Ethernet
  • Low Latency, 19.2ns at 64-Bit at 156.25MHz
  • AXI4-Stream protocol support on client transmit and receive interface
  • Low resource usage
  • Deficit Idle Count mechanism to ensure full data rate
  • Padding of short frames (<64 byte)
  • Support for VLAN tagged frames
  • Promiscuous mode support
  • Generation and checking of CRC-32 at full line rate
  • Optional user defined maximum frame length up to 64 kb or complete disabling of frame length check
  • Customization through configuration vector to trade resources for functionality
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® III FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Fully paid-up-for Single-Project or Multi-Project Use IP Core license for FPGA; delivered as encrypted netlist or RTL.

Ordering Information

Market Segment and Sub-Segments