MIPI CSI-2 Receive Core

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Foresys Inc

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This MIPI CSI-2 Receive core seamlessly integrates with Altera's Avalon interface or directly interfaces to custom logic. It is a lightweight core, able to fit in even smaller MAX® 10 devices. Multiple cores can be instantiated into a single FPGA. Foresys fully supports the core and ensures that each engagement is successful.

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Key Features

Configurable 1, 2, or 4 lanes
Multiple instantiations possible
Resource friendly
Fully Supported

Offering Brief

Device Family	Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	25.1.0
Development Language	Encrypted Verilog, Encrypted VHDL