PCIe Gen 5

Overview Key Features Offering Brief What's Included Ordering Information Markets

Qbit Labs Incorporation

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The PCIe Gen 5 offering provides a high-performance, standards-compliant connectivity solution delivering data rates up to 32 GT/s per lane for bandwidth-intensive applications. It is designed to support next-generation servers, accelerators, storage subsystems, and embedded platforms requiring low latency, high throughput, and reliable data transfer. The solution enables scalable system architectures with backward compatibility to earlier PCIe generations and supports robust integration into modern data center, AI, and high-performance computing environments.

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Key Features

PCI Express 5.0 Compliant: Fully adheres to the latest PCIe 5.0 Base Specification, ensuring reliable compatibility and functionality.
High-Speed Performance: Supports 32 GT/s per lane, achieving an aggregate throughput of up to 512 GT/s in x16 lane configuration.
Flexible Lane Configurations: Configurable for x1, x2, x4, x8, and x16 lanes to suit a broad range of performance and cost targets.
Backward Compatibility: Compatible with PCIe Gen 1/2/3/4, ensuring smooth integration in mixed-generation environments.
Robust Data Handling: Features built-in DMA engine, AXI4/AXI4-Stream interfaces, transaction layer packet handling, and retry/flow control logic.
Error Detection & Recovery: Includes Advanced Error Reporting (AER), ECC, LTSSM, and replay buffers for maximum data integrity.

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status	Production
Integrated Testbench	No
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog

Synthesizable encrypted RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset.

Embedded firmware / low-level SW

Software integration guide

Full design documentation

FPGA bitstream/prototyping support