MIPI CSI-2

Overview Key Features Offering Brief What's Included Ordering Information Markets

Qbit Labs Incorporation

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Qbit Labs’ MIPI CSI-2 IP Core and Controller provides high-speed, low-power image sensor connectivity for modern imaging and vision systems. Fully compliant with the MIPI CSI-2 standard, it supports scalable, reliable data transfer from camera sensors with low latency and efficient bandwidth utilization. Designed for easy integration on FPGA and SoC platforms, the solution enables flexible camera interface implementation for AI/ML vision, automotive imaging, industrial inspection, and embedded vision applications, helping reduce integration effort and accelerate time-to-market.

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Key Features

Standards Compliant – Fully supports MIPI CSI-2 v4.0 with C-PHY and D-PHY integration
High Performance – Supports up to 4 data lanes with multi-virtual-channel capability (up to 16 VCs in D-PHY and 32 VCs in C-PHY) and broad pixel format compatibility
Robust Data Handling – Built-in error detection, ECC, scrambling, compression (DSC), and data interleaving support
Seamless Integration – AXI4-Stream for pixel data and AXI4-Lite for control, enabling easy SoC and FPGA integration

Offering Brief

Device Family	Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status	Production
Integrated Testbench	No
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog