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MIPI DP 2.0

Qbit Labs Incorporation

Member

The MIPI DisplayPort 2.0 IP Core is a next-generation high-speed display interface IP solution designed to meet the increasing demands for ultra-high-resolution video, multi-stream support, and power efficiency across a broad spectrum of devices.

Built on the latest DisplayPort 2.0 specification from the Video Electronics Standards Association (VESA), it delivers enhanced data bandwidth, flexible protocol layers, and superior display quality—all while supporting MIPI PHY standards such as M-PHY for mobile and embedded applications.

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Key Features

  • Supports SST as well as MST to split streams for daisy chaining multiple displays.
  • Supports DSC 1.2a for lossless compression for very high resolutions.
  • Multiple displays over single cable with independent timing streams in MST.
  • 1Mbps bidirectional Aux sideband channel for control/EDID/DPCD.
  • Secondary packet can be inserted during blanking intervals- Audio, Info frame, HDCP, PPS, Vendor specific.
  • Supports 4 Lanes upto 20.0Gbps (UHBR20) and Hot Plug detection through Aux channel.
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Reference design and integration guidelines

User documentation and configuration guide

Basic testbench and validation support

Technical support during integration

Synthesizable RTL source code

Ordering Information

QB-IP-MIPI-DP-2.0

from Direct

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