MIPI H.264

Overview Key Features Offering Brief What's Included Ordering Information Markets

Qbit Labs Incorporation

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The MIPI H.264 IP Core is a high-performance, low-latency video encoder/decoder solution designed for real-time video compression and decompression based on the ITU-T H.264 / MPEG-4 AVC standard.

This IP core is optimized for efficient integration with MIPI camera (CSI-2) and display (DSI-2) interfaces, offering seamless support for high-resolution imaging and display systems in mobile, automotive, AR/VR, surveillance, and embedded applications.

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Key Features

Compliant with H.264/AVC Standard (ISO/IEC 14496-10): Supports Baseline, Main, and High Profiles up to Level 5.1
Real-Time Encoding and Decoding: High frame rate supports up to 4K @ 60fps Ultra-low latency pipeline for live-streaming and real-time video applications
Seamless MIPI Interface Integration: Native support for MIPI CSI-2 (input) and DSI-2 (output) protocols Compatible with MIPI PHYs including D-PHY and C-PHY
Flexible Buffer Management: Internal frame buffer and external DDR interfacing for large video streams
Low Power Support: Clock gating and power-down modes integrated for mobile platforms

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
OS Support	Linux, Android, RTOS
Development Language	Encrypted Verilog, Verilog

Synthesizable RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset

Embedded firmware / low-level SW

Software integration guide

Full design documentation