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DVB-S2 IP

Qbit Labs Incorporation

Member

A DVB-S2 (Digital Video Broadcasting – Satellite – Second Generation) IP Core is a highly optimized digital baseband processing solution designed to implement the physical layer functions required for modern satellite communication systems. This IP core enables efficient transmission of high-quality video, audio, and data services over satellite networks by supporting advanced modulation and coding techniques defined in the DVB-S2 standard. It typically incorporates powerful Forward Error Correction (FEC) mechanisms such as Low-Density Parity-Check Code (LDPC) and Bose–Chaudhuri–Hocquenghem Code (BCH) to ensure reliable data transmission even under challenging channel conditions. The IP core supports multiple modulation schemes including Phase Shift Keying (QPSK/8PSK) and Amplitude and Phase-Shift Keying (APSK), enabling adaptive coding and modulation to maximize spectral efficiency and throughput. Designed for integration into Field-Programmable Gate Array (F...

A DVB-S2 (Digital Video Broadcasting – Satellite – Second Generation) IP Core is a highly optimized digital baseband processing solution designed to implement the physical layer functions required for modern satellite communication systems. This IP core enables efficient transmission of high-quality video, audio, and data services over satellite networks by supporting advanced modulation and coding techniques defined in the DVB-S2 standard. It typically incorporates powerful Forward Error Correction (FEC) mechanisms such as Low-Density Parity-Check Code (LDPC) and Bose–Chaudhuri–Hocquenghem Code (BCH) to ensure reliable data transmission even under challenging channel conditions. The IP core supports multiple modulation schemes including Phase Shift Keying (QPSK/8PSK) and Amplitude and Phase-Shift Keying (APSK), enabling adaptive coding and modulation to maximize spectral efficiency and throughput. Designed for integration into Field-Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) platforms, the DVB-S2 IP core provides configurable frame processing, symbol mapping, interleaving, and baseband framing while supporting features such as adaptive coding and modulation (ACM) and variable coding and modulation (VCM). This flexibility makes it ideal for satellite broadcasting, broadband satellite internet, professional video distribution, and other high-capacity satellite communication applications, delivering robust performance, efficient bandwidth utilization, and seamless integration into next-generation satellite infrastructure.

Key Features

  • Full DVB-S2 Compliance: Implements ETSI EN 302 307 standard supporting QPSK, 8PSK, 16APSK, and 32APSK modulation schemes.
  • LDPC and BCH FEC Encoder/Decoder: Highly optimized Forward Error Correction with concatenated LDPC and BCH coding for excellent noise resilience and performance near Shannon limit.
  • ACM/VCM Support: Supports Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM) for dynamic bandwidth adaptation based on channel conditions.
  • Multi-Stream Transmission: Enables efficient bandwidth use by multiplexing multiple transport streams over a single carrier using ISI (Input Stream Identifier).
  • Configurable Code Rates: Supports multiple code rates (1/4 to 9/10), customizable according to link requirements.
  • Standardized Interfaces: AXI4-Stream, Avalon-ST, or custom interface options available for integration with host processing systems or transport stream engines.
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Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Synthesizable RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset

Embedded firmware / low-level SW

Software integration guide

Full design documentation

Ordering Information

Market Segment and Sub-Segments