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LDPC IP

Qbit Labs Incorporation

Member

LDPC IP (Low-Density Parity-Check Intellectual Property) is a high-performance forward error correction (FEC) solution designed to significantly improve data reliability in high-speed digital communication systems. The IP core implements advanced LDPC encoding and decoding algorithms that detect and correct transmission errors caused by noise, interference, or signal degradation. It supports configurable code rates, block lengths, and throughput options, enabling flexible integration into FPGA or ASIC-based systems. The LDPC IP is optimized for low latency, efficient hardware utilization, and high data throughput, making it suitable for applications such as satellite communications, wireless networks, broadband systems, and next-generation communication standards. Its scalable architecture allows seamless adaptation to different system requirements while maintaining robust error-correction performance.

Key Features

  • Ultra-High Throughput: Achieves data rates exceeding multi-Gbps in parallel decoder configurations, with scalability for even higher throughput.
  • Flexible Code Support: Supports standard-compliant codes (e.g., 5G, DVB-S2, 802.11ax) and customizable LDPC matrices for proprietary use cases.
  • Multiple Decoding Algorithms: Includes Min-Sum, Normalized Min-Sum, Offset Min-Sum, and layered decoding approaches for performance and area trade-offs.
  • Programmable Block Sizes & Code Rates: Dynamic configuration of codeword length (up to 64K) and code rates (from 1/4 to 9/10) without re-synthesis.
  • Soft Decision Input Support: Operates on LLR (Log-Likelihood Ratio) inputs for improved decoding performance over noisy channels.
  • Fully Parameterizable Architecture: Allows selection of the number of iterations, input width, memory organization, and throughput level during synthesis.
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Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Synthesizable RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset

Embedded firmware / low-level SW

Software integration guide

Full design documentation

Ordering Information

Market Segment and Sub-Segments