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Cryptographic Accelerator

Eideticom’s Cryptographic Accelerator is a security platform designed to accelerate public key cryptography in datacenter environments. It supports both classical and post-quantum cryptographic (PQC) algorithms and is built to help cloud service providers (CSPs) and content delivery networks (CDNs) transition to PQC while maintaining performance and security. Our Cryptographic Accelerator ensures secure key management while significantly enhancing overall system performance. Eideticom’s Cryptographic Accelerator utilizes ML-KEM (FIPS 203) and ML-DSA (FIPS 204), ensuring support for NIST-approved post-quantum cryptographic standards.

By Eideticom

CSENT-Rx: SENT/SAE J2716 Receiver

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. A set of handshaking signals facilitates the integration with an external DMA controller. The CSENT-RX core is designed with industry best practice, has been rigorously verified and is production proven.

By Computer Aided Software Technologies, Inc (dba CAST)

CTAccel Image Processing (CIP) Accelerator

By CTAccel Limited

Current: xSPI Initiator core.  

xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.

By Synaptic Laboratories Ltd

Custom Development: from Requirements over Specification, Design, Architecture Implementation and Verification to Deployment.

NetTimeLogic provides design services in the areas of FPGA and embedded software development, especially in the areas of time synchronization and network redundancy. From requirements engineering over custom IP core development, OS porting, drivers, GUIs and testing to education and consulting, we can help you to bring your system to a success. We develop FPGA firmware in VHDL and Verilog. From simple entities to complete IP core solution we can help you in every step of FPGA development

By NetTimeLogic GmbH

CXL 3.x

The Compute Express Link™ (CXL) 3.x IP Core is designed to meet the demands of next-generation heterogeneous computing systems, enabling high-speed, low-latency interconnect between CPUs, GPUs, FPGAs, DPUs, accelerators, memory expanders, and smart I/O devices.

By Qbit Labs Incorporation

CXL Tester

Mobiveil’s CXL Tester is designed to validate Compute Express Link interfaces including CXL.io, CXL.cache, and CXL.mem protocols. It supports the testing of high-performance accelerators and memory expanders over PCIe Gen5/Gen6. The solution utilizes Altera FPGAs to deliver a scalable and adaptable test environment.

By Mobiveil Inc.

Cyclone® 10 GX FPGA Development Kit

The Cyclone® 10 GX Development Kit is a cost-effective platform for transceiver-based applications, featuring high-speed I/O and robust memory support.

By Altera

Cyclone® 10 LP FPGA Development Kit

The Cyclone® 10 LP Evaluation Kit is a low-cost, low-power platform ideal for entry-level FPGA development and education.

By Altera