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HAN Pilot Platform

Terasic’s HAN Pilot Platform is a high-performance flagship development kit based on Intel Arria 10 SoC FPGAs. With the goal of “being the pilot platform for HPC, Automotive, and Networking applications (HAN),” the board is purpose built for performance-demanding industrial embedded applications.

HawkEye-20GigE: 20 GigE Vision Frame Grabber & Image Processing\Smart NIC

HawkEye-20GigE Vision Dual-Port 10 GigE Frame Grabbing & Image Processing System\Smart NIC. The HawkEye-20 GigE Frame Grabber is ideal for high performance, high-bandwidth applications based on multiple cameras and/or ultra-high bandwidth cameras.  The HawkEye-20GigE's real-time FPGA processing ensures zero frame loss and virtually zero CPU utilization, freeing the CPU for key processing tasks. 

HawkEye-CL: Camera Link Frame Grabber & Image Processing

The HawkEye-CL Frame Grabber is Camera Link Rev. 2.0 compliant, offering a number of options, from plug-and-play grabbers to a full system solution that includes acquisition and on-FPGA processing. The card is supported by off-the-shelf modular building blocks for embedding in the acquisition pipeline, including HDR, white balance, gamma correction, compression (JPG, lossless, Quality+), and more. It is also supported by Gidel's InfiniVision acquisition architecture, optimized for grabbing from 100+ cameras.

HawkEye-CXP12: CoaXPress-12 Frame Grabber & Image Processing

The HawkEye-CXP12 is a 4 x CoaXPress-12 Frame Grabber card with option for real-time image processing and compression. The card is supported by off-the-shelf modular building blocks for embedding in the acquisition pipeline, including HDR, white balance, gamma correction, compression (JPG, lossless, Quality+), and more. It is also supported by Gidel's InfiniVision acquisition architecture, optimized for grabbing from 100 + cameras

HBM2E (High-Bandwidth Memory) FPGA IP

HBM2E is a high-performance memory IP that offers a combination of high memory bandwidth, low power consumption, low latency, and small form factor for Agilex™ 7 FPGA M-Series devices. HBM2E memory is well-suited for various high-performance computing applications.

HDMI IP Core

The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.

HDMI-FMC Daughter Card

Terasic HDMI-FMC is a HDMI transmitter/receiver daughter board with FMC (FPGA Mezzanine card) interface. The user can connect the HDMI module with the FPGA development kit via the FMC connector for HDMI image & video capturing, processing and displaying up to 4Kx2K@30fps resolution.

HDR MODEM

A High Data Rate (HDR) modem enables reliable transmission of large volumes of data over communication channels with high efficiency. In the transmitter, the input data packet is first protected using CRC, then divided into smaller blocks and encoded using powerful forward error correction such as Low-Density Parity-Check Code. The encoded data undergoes rate matching and interleaving to improve robustness against channel errors before transmission. At the receiver, the process is reversed: the received soft information is deinterleaved, rate-adapted, and decoded using LDPC decoding. Finally, a CRC check verifies the correctness of the recovered data, ensuring reliable high-speed communication.

Heronic AI Accelerator Design Services

Heronic Technologies offers specialized design services for bespoke AI accelerator architectures on FPGAs, utilizing in-house automation and an IP portfolio to meet the unique demands of diverse AI applications like object detection and image classification. This approach directly tackles the inefficiency of generalized hardware in Edge AI and TinyML, enabling the rapid development of highly efficient, streaming-based accelerators. As a result, Heronic delivers unparalleled performance and microsecond latency, evidenced by state-of-the-art results on MLPerf Tiny and superior outcomes compared to GPU offerings.