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Agilex™ 3 FPGA C-Series
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eASIC™ N3X Devices
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Agilex® 3 FPGAs and SoC FPGAs C-Series
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Arria® 10 GT FPGA
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Company Name

By Source

Altera Solutions
Partner Solutions

Offering Types

Acceleration / AI / Cloud
- Artificial Intelligence (AI)
- Data Processing / Analysis / Acquisition
- Data Science
- Edge
- Machine Learning
- Neural Network
- Public / On Premise
- Regional / District / Central
- Storage / Compression
Boards / SOMs / Dev Kits
- COTS
- Daughter Card
- Development / Evaluation Kit
- DPU / IPU / AI NIC / SmartNIC
- PCI Express
- System-on-Module (SOM)
- VPX
Design Services
- Board Level Design (DS)
- Certification (DS)
- Custom IP (DS)
- Debug (DS)
- Design for Manufacturing (DS)
- FPGA Design (DS)
- Logistics (DS)
- Manufacturing (DS)
- Schematic / Layout Review & DFT (DS)
- SI / PI Simulation (DS)
- Software (DS)
- System Level Design (DS)
- Verification / Validation (DS)
EDA Tools / IDE
- Design
- Embedded Tools
- Protocol Analysis
- Simulation
- Verification
Education / Training
- Acceleration / Artificial Intelligence (AI)
- Design Optimization
- Digital Signal Processing
- Embedded Processing
- External Memory Interfaces
- HDL Design Methodologies
- Interface Protocols
- Quartus Design Flow
- Security
Intellectual Property (IP)
- Digital Signal Processing / AI
  - Artificial Intelligence
  - Error Correction
  - Filters /Transforms
  - Floating Point
  - Modulation
  - Video and Image Processing
- Interfaces
  - Audio / Video
  - Communication
  - Compute Express Link (CXL)
  - Ethernet
  - High Speed
  - Networking / Security
  - PCI Express (IP)
  - Serial
- Memory Controllers
  - DMA
  - Flash
  - SDRAM
  - SRAM
- Soft Embedded Processors
  - RISC V
- Transceivers & Basic Functions
  - Clocks, PLLs and Resets
  - Simulation, Debug and Verification
  - Transceivers
Manufacturer
- Board Level Design (MF)
- Certification (MF)
- Custom IP (MF)
- Debug (MF)
- Design for Manufacturing (MF)
- FPGA Design (MF)
- Logistics (MF)
- Manufacturing (MF)
- Schematic / Layout Review & DFT (MF)
- SI / PI Simulation (MF)
- Software (MF)
- System Level Design (MF)
- Verification / Validation (MF)
Software / OS / RTOS
- Drivers
- Embedded
- Operating System (OS)
- Real Time Operating System (RTOS)
System Integrator / Provider
- Board Integration
- Chassis construction
- Chip Integration
- Software Integration

Region

Americas
Asia Pacific
Europe & Middle East
Japan
People’s Republic of China

Device Family

Agilex™ 3 FPGA C-Series
Agilex™ 5 FPGA D-Series
Agilex™ 5 FPGA E-Series
Agilex™ 7 FPGA F-Series
Agilex™ 7 FPGA I-Series
Agilex™ 7 FPGA M-Series
Agilex™ 9 FPGA Direct RF-Series
Arria® 10 Bare Die
Arria® 10 GT FPGA
Arria® 10 GX FPGA
Arria® 10 SX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V ST FPGA
Arria® V ST SoC FPGA
Arria® V SX FPGA
Arria® V SX SoC FPGA
Cyclone® 10 GX FPGA
Cyclone® 10 LP FPGA
Cyclone® II FPGA
Cyclone® III Bare Die
Cyclone® III FPGA
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Cyclone® V E FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V SE FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX FPGA
Cyclone® V SX SoC FPGA
eASIC™ N3X Devices
eASIC™ N3XS Devices
eASIC™ N5X Devices
Agilex® 3 FPGAs and SoC FPGAs C-Series
Agilex® 5 FPGAs and SoC FPGAs D-Series
Agilex® 5 FPGAs and SoC FPGAs E-Series
Agilex® 7 FPGAs and SoC FPGAs F-Series
Agilex® 7 FPGAs and SoC FPGAs I-Series
Agilex® 7 FPGAs and SoC FPGAs M-Series
Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series
Arria® 10 GT FPGA
Arria® 10 GX FPGA
Arria® 10 SX SoC FPGA
Cyclone® 10 GX FPGA
Cyclone® 10 LP FPGA
eASIC® N3X Devices
eASIC® N3XS Devices
eASIC™ N3X Devices
eASIC™ N3XS Devices
MAX® 10 FPGA
Stratix® 10 AX SoC FPGA
Stratix® 10 DX FPGA
Stratix® 10 GX FPGA
Stratix® 10 SX SoC FPGA
Stratix® 10 TX FPGA
MAX® 10 FPGA
MAX® II CPLD
MAX® II Z CPLD
MAX® V CPLD
Mustang Mesa
Stratix® 10 AX FPGA
Stratix® 10 Bare Die
Stratix® 10 DX FPGA
Stratix® 10 GX FPGA
Stratix® 10 SX FPGA
Stratix® 10 TX FPGA
Stratix® III FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA

Market Segments

Access
- Cable Access
- Carrier Access
- Other Access
Aerospace
- Aerospace
ASIC Proto
- ASIC Emulation
- ASIC Prototyping
Broadcast
- Broadcast Studio
- ProAV
Consumer
- Gaming
- Home Audio/Video
- Multi-Functional Printer
- Other Consumer
Defense
- MIL COMMS
- Radar/Ew
Industrial
- Energy
- Industrial / Manufacturing
- Robotics
- Vision
Government
- Chassis construction
- Drivers
- Govt Infrastructure
- Other ADG
- Software Integration
Medical
- Imaging
- Lab/Life Sciences
- Non-Imaging Patient Devices
- Other Medical
- Ultrasound
- Video
Data Center OEM (IHV, ISV, SI, VAR)
- AI/HPC
- CDNs
- IaaS/PaaS
- Networking
- Storage
- Transmission
Transportation
- Automotive (Passenger Vehicles)
- Non-Automotive Transportation
- Charging Infrastructure
- Transportation Infrastructure (non-charging)
Data Center Cloud (Public, Private, Hybrid)
- AI/HPC
- IaaS/PaaS
- Networking
- CDNs
- Storage
- Transmission
Wireless
- Baseband
- AI-RAN
- NTN/Fixed Wireless
- DAS/repeater/RIS
- xhaul Hub
- RDU
- FWA/backhaul
- 5G/ 6G Radio
Test
- ATE
- RF Instrumentation
- Communication Tester
- Other Test

Program Level

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50G Ethernet FPGA IP

The 50G Ethernet FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and PMA functions. The PHY comprises the PCS and PMA.

By Altera

View Details

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

MLE 50G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 50Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full duplex data width, and pipelines all-RTL implementation for high throughput and ultra low Latency.

By Missing Link Electronics

View Details

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 50G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

By Missing Link Electronics

View Details

5G LDPC-V FPGA IP

Low-density parity-check (LDPC) IP helps transmit and receive messages over noisy channels. This IP implements LDPC codes compliant with the 3rd generation partnership project 5G specification.

By Altera

View Details

800G Ethernet IP core

800G IP core for Agilex™ 7 I/M series FPGAs with 112Gbps transceivers. ETC-compliant 800Gbps Ethernet for networks, switches, and NICs using eight 112Gbps lanes and a single 800G MAC.

By Hitek Systems LLC

View Details

802.11ax

The 802.11ax (Wi-Fi 6) IP Core is a next-gen wireless solution built for high-throughput, low-latency, and dense networks. Fully compliant with IEEE 802.11ax, it features OFDMA, MU-MIMO, 1024-QAM, and Target Wake Time.

By Qbit Labs Incorporation

View Details

Achieving Timing Closure

The most comprehensive timing training which deals with simple and very complex, low and high speed timing violation. Write complex SDC files for advanced use cases. Analyze timing violation and apply a solution from an arsenal of options. Use the device architecture and tricks to solve complex issues.

By HandsOn-Training

View Details

Adjustable Clock

Full standalone hardware only solution of an adjustable Counter Clock

By NetTimeLogic GmbH

View Details

AES - Advanced Encryption Standard Engine

The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (CBC, CFB, CTR, ECB, LRW, and OFB). The core works with a pre-expanded key, or with optional key expansion logic. The AES core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs, with complete deliverables.

By Computer Aided Software Technologies, Inc (dba CAST)

View Details

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50G Ethernet FPGA IP

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

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802.11ax

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50G Ethernet FPGA IP

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

5G LDPC-V FPGA IP

800G Ethernet IP core

802.11ax

Achieving Timing Closure

Adjustable Clock

AES - Advanced Encryption Standard Engine